Evaluation of write-back caches for multiple block-sizes

Trace-driven simulation of cache memories usually requires enormous disk space to store CPU trace data. On-the-fly simulation avoids this problem by running the simulation while the trace data is being generated. For write-back least-recently-used (LRU) caches, we propose an on-the-fly simulation method, which is a variant of the standard one-pass stack evaluation techniques that evaluates write ratios for multiple block-sizes in a one-pass processing of trace data. It is known that for LRU cache memories, the hit ratios can be found for multiple block-sizes in one-pass trace processing; and for write-back caches, the write ratios can be found for a single block size in one-pass trace processing. Combining these two techniques, this paper proposes a simple one-pass method for write-back LRU caches that evaluates write ratios for multiple block-sizes