Title :
A 22dB PSRR enhancement in a two-stage CMOS opamp using tail compensation
Author :
Furth, Paul M. ; Pakala, Sri Harsh ; Garimella, Annajirao ; Mohan, Chaitanya
Author_Institution :
VLSI Lab., New Mexico State Univ., Las Cruces, NM, USA
Abstract :
A new compensation technique known as tail compensation is applied to a two-stage CMOS operational amplifier. The compensation is established by a capacitor connected between the output node and the source node of the differential amplifier. For the selected opamp topology, tail compensation allows better performance in terms of bandwidth and power supply rejection ratio (PSRR) when compared to Miller and cascode compensation. Operational amplifiers using Miller, cascode and tail compensation were fabricated in a 0.5-μm 2P3M CMOS process. The circuits operate at a total quiescent current of 90 μA with ±1.5V power supplies. Experimental results show that tail compensation increases the unity-gain frequency by 60% and 25% and improves PSRR from the positive rail by 22 dB and 26 dB over a frequency range from 23 kHz to 3.0 MHz compared to Miller and cascode compensation, respectively.
Keywords :
CMOS analogue integrated circuits; capacitors; differential amplifiers; network topology; operational amplifiers; Miller compensation; PSRR enhancement; capacitor; cascode compensation; current 90 muA; differential amplifier; frequency 23 kHz to 3 MHz; output node; power supply rejection ratio; selected opamp topology; size 0.5 mum; source node; tail compensation; two-stage CMOS opamp; two-stage CMOS operational amplifier; CMOS integrated circuits; Capacitors; Mathematical model; Noise; Power supplies; Transconductance; Transistors; Miller compensation; Tail compensation; power supply rejection ratio; two-stage opamps;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4673-1555-5
Electronic_ISBN :
0886-5930
DOI :
10.1109/CICC.2012.6330669
