Title :
Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors
Author :
Paul, Ayan ; Amrein, Matt ; Gupta, Saket ; Vinod, Arvind ; Arun, Abhishek ; Sapatnekar, Sachin ; Kim, Chris H.
Author_Institution :
Univ. of Minnesota, Minneapolis, MN, USA
Abstract :
In order to reduce the impact of resonant supply noise on processor performance, a simple, fully-digital and scalable technique based on staggering the activation time of the cores sharing the same power domain in a multi-core multi-power domain processor is presented. Measurement data from a 65nm test chip shows an Fmax improvement as large as 20% in a 3-core configuration. This is one of the first approaches to utilize the architecture level behavior for mitigating resonant noise issues in a multi-core multi-power domain processor.
Keywords :
circuit noise; computer architecture; multiprocessing systems; 3-core configuration; architectural approach; architecture level behavior; circuit approach; multicore multipower domain processor; power domain sharing; processor performance; resonant supply noise mitigation; simple fully-digital scalable technique; staggered core activation; Bit error rate; Delay; Multicore processing; Noise; Program processors; Semiconductor device measurement; System-on-a-chip;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4673-1555-5
Electronic_ISBN :
0886-5930
DOI :
10.1109/CICC.2012.6330673
