Towards the automatic derivation of computer performance models from the real time and embedded systems design

Real-time and embedded systems always have performance constraints. With conventional design techniques, these constraints are verified at the testing phase and the designer does no performance constraint estimation during the design. From the design information, it is possible to deduce a queueing network performance model, but its execution requires supplementary information concerning estimations of the execution times. Delays generated by logical locking and by resource use conflicts can be computed, via analytical or simulation techniques, from such a model. This paper presents experience acquired in the integration of design methods and the performance modelling techniques