DocumentCode :
1807035
Title :
A mixed-mode FPAA SoC for analog-enhanced signal processing
Author :
Schlottmann, Craig ; Nease, Stephen ; Shapero, Samuel ; Hasler, Paul
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear :
2012
fDate :
9-12 Sept. 2012
Firstpage :
1
Lastpage :
4
Abstract :
We present the RASP 2.9v, an FPAA for mixed-signal computation with an emphasis on enhanced digital support. This 25mm2, 350nm CMOS chip includes on-chip compilable DACs, dynamic reconfigurability and digital storage, and 76,000 programmable elements. We demonstrate an analog image-transform processor, an arbitrary waveform generator, and a mixed-mode FIR filter.
Keywords :
CMOS integrated circuits; digital signal processing chips; field programmable analogue arrays; system-on-chip; CMOS chip; RASP 2.9v; analog image-transform processor; analog-enhanced signal processing; digital storage; dynamic reconfigurability; field programmable analog arrays; mixed-mode FIR filter; mixed-mode FPAA SoC; mixed-signal computation; on-chip compilable DAC; size 350 nm; waveform generator; Computer architecture; Field programmable analog arrays; Finite impulse response filter; Registers; Switches; Switching circuits; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location :
San Jose, CA
ISSN :
0886-5930
Print_ISBN :
978-1-4673-1555-5
Electronic_ISBN :
0886-5930
Type :
conf
DOI :
10.1109/CICC.2012.6330679
Filename :
6330679
Link To Document :
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