A self-checking cell logic block for fault tolerant FPGAs

This paper proposes a self-checking Cell Logic Block (CLB) that can be used as building block for on-line testable FPGAs. The proposed cell consists, basically, of a 4 input Look-Up-Table (LUT) and a D flip-flop. The CLB is designed using pass-transistor-based multiplexers, either to select the output of the 4-input LUT, or to select signals from other CLBs. The proposed CLB architecture is characterized by a simple circuit to detect incorrect logic voltage levels due to stuck-close and stuck-open faults and by a sensor to test anomalous dissipated currents. In this way, the proposed CLB allows on-line detection of any single transistor fault.