A self-checking cell logic block for fault tolerant FPGAs

Author

Pontarelli, S. ; Cardarilli, G.C. ; Leandri, A. ; Ottavi, M. ; Re, M. ; Salsano, A.

Author_Institution

Dept. of Electron. Eng., Rome Univ., Italy

Volume

4

fYear

2002

fDate

2002

Abstract

This paper proposes a self-checking Cell Logic Block (CLB) that can be used as building block for on-line testable FPGAs. The proposed cell consists, basically, of a 4 input Look-Up-Table (LUT) and a D flip-flop. The CLB is designed using pass-transistor-based multiplexers, either to select the output of the 4-input LUT, or to select signals from other CLBs. The proposed CLB architecture is characterized by a simple circuit to detect incorrect logic voltage levels due to stuck-close and stuck-open faults and by a sensor to test anomalous dissipated currents. In this way, the proposed CLB allows on-line detection of any single transistor fault.

Keywords

CMOS logic circuits; automatic testing; fault tolerance; field programmable gate arrays; integrated circuit reliability; integrated circuit testing; logic testing; table lookup; 4-input lookup table; D flip-flop; anomalous dissipated currents; current sensor; fault tolerant FPGAs; online detection; online testable FPGAs; pass-transistor-based multiplexers; self-checking cell logic block; stuck-close faults; stuck-open faults; transistor fault; Automatic testing; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Fault tolerance; Field programmable gate arrays; Flip-flops; Logic testing; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010496

Filename

1010496