Interconnect peak current reduction for wavelet array processor using self-timed signaling

This paper describes a method for reducing the interconnection peak current in a system-on-chip design. The method is applied to a globally asynchronous locally synchronous 128-point wavelet processor array design with 1.45 million equivalent gates. In the proposed approach, data transfer along buffered highly capacitive on-chip interconnects is realized using asynchronous communication channels. These channels are managed by a global self-timed controller which allows only one channel to be active at a time. This method reduces the interconnect peak current by 75% compared to a design where wires are driven synchronously. This approach allows the reduction of the area devoted to the decoupling capacitance needed to suppress power supply noise.