Integration of unlanded via in a non-etchback SOG direct-on-metal approach in 0.25 micron CMOS process

Author

Gao, T. ; Coenegrachts, B. ; Waeterloos, J. ; Beyer, G. ; Meynen, H. ; Van Hove, M. ; Maex, K.

Author_Institution

IMEC, Heverlee, Belgium

fYear

1998

fDate

1-3 Jun 1998

Firstpage

45

Lastpage

47

Abstract

A novel approach of via integration with nonetchback (NEB) SOG is investigated to improve performance of unlanded vias, which is a serious problem if zero-overlap metal lines are used. The improvement is attributed to the larger contact area between the unlanded via and the underlying metal line. The direct-on-metal (DOM) technique is applied in order to achieve a superior contact between the via plug and the underlying metal line, even for a large misalignment. Several integration issues related to DOM and unlanded vias are discussed

Keywords

CMOS integrated circuits; dielectric thin films; glass; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; spin coating; CMOS process; contact area; direct-on-metal technique; integration issues; metal line; nonetchback SOG; nonetchback SOG direct-on-metal method; unlanded via integration; unlanded vias; via integration; via plug; via-line misalignment; zero-overlap metal lines; Artificial intelligence; Atherosclerosis; CMOS process; CMOS technology; Dielectric materials; Etching; Metals industry; Plugs; Sputtering; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 1998. Proceedings of the IEEE 1998 International

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-4285-2

Type

conf

DOI

10.1109/IITC.1998.704747

Filename

704747