Title :
A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS
Author :
Kaviani, Kambiz ; Hossain, Masum ; Nazari, Meisam Honarvar ; Heaton, Fred ; Ren, Jihong ; Zerbe, Jared
Author_Institution :
Rambus Inc., Sunnyvale, CA, USA
Abstract :
A new 1-tap predictive decision feedback equalizer (prDFE), implemented in 40-nm CMOS LP process, achieves 27-Gb/s operation with 0.41-mW/Gb/s power efficiency. The prDFE employs a novel quad-data rate sampling architecture to improve power efficiency while minimizing critical feedback path timing constraint of the equalizer to enable post-cursor inter-symbol interference (ISI) cancellation at high data-rate operations.
Keywords :
CMOS integrated circuits; decision feedback equalisers; interference suppression; intersymbol interference; low-power electronics; sampling methods; CMOS LP process; ISI cancellation; bit rate 27 Gbit/s; critical feedback path timing constraint; high data-rate operations; low-power CMOS; post-cursor intersymbol interference cancellation; power efficiency; prDFE; predictive decision feedback equalizer; quad-data rate sampling architecture; size 40 nm; CMOS integrated circuits; Calibration; Clocks; Decision feedback equalizers; Feedback loop; Multiplexing; Timing;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4673-1555-5
Electronic_ISBN :
0886-5930
DOI :
10.1109/CICC.2012.6330684
