Title :
A built-in self-testing method for embedded multiport memory arrays
Author :
Narayanan, V. ; Ghosh, S. ; Jone, W.B. ; Das, S.R.
Author_Institution :
ECECS Dept., Cincinnati Univ., OH, USA
Abstract :
Multiport memories are widely used in multiprocessor systems, telecommunication ASICs etc. Research papers which define multi-port memory fault models and give march tests for the same are currently available. However, little work, has been done to use the power of serial interfacing for testing multi-port memories. In this paper we discuss some basics about the architecture of two-port memories and fault models for the same. We have then used the serial testing mechanism to propose new algorithms which can prove effective to reduce the hardware cost considerably on a chip with many multi-port memories. Once the serial interfacing for two-port memory testing is understood, it can be extended for p-port memories (p>2). The proposed method based on the serial interfacing technique has the advantages of high fault coverage, low hardware overhead and tolerable test application time.
Keywords :
CMOS memory circuits; VLSI; built-in self test; fault simulation; integrated circuit testing; multiport networks; random-access storage; system-on-chip; built-in self-testing method; embedded multiport memory arrays; fault models; hardware cost; high fault coverage; low hardware overhead; serial interfacing; serial scan circuit; system-on-chip; tolerable test application time; two-port memories; Built-in self-test; CMOS logic circuits; Circuit faults; Circuit testing; Hardware; Information technology; Random access memory; Read-write memory; Space technology; System-on-a-chip;
Conference_Titel :
Instrumentation and Measurement Technology Conference, 2004. IMTC 04. Proceedings of the 21st IEEE
Print_ISBN :
0-7803-8248-X
DOI :
10.1109/IMTC.2004.1351487
