Title :
A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC
Author :
Wong, Si-Seng ; Chio, U-Fat ; Zhu, Yan ; Sin, Sai-Weng ; U, Seng-Pan ; Martins, R.P.
Author_Institution :
State-Key Lab. of Analog & Mixed Signal VLSI, Univ. of Macau, Macao, China
Abstract :
A 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC architecture is proposed, where the ADC´s front-end is built with a 5b binary-search ADC, shared by two time-interleaved 6b SAR ADCs in the 2nd-stage. The design prevents the use of opamp that causes large power dissipation. Besides, a process insensitive asynchronous logic is proposed to further reduce the delay of SA loop. The ADC was fabricated in 65nm CMOS and achieves 54.6dB SNDR at 170MS/s with only 2.3mW of power consumption, leading to a FoM of 30.8fJ/conversion-step.
Keywords :
CMOS integrated circuits; analogue-digital conversion; asynchronous circuits; cooling; nanoelectronics; operational amplifiers; 5b binary-search ADC; ADC front-end; CMOS; SA loop; opamp; power 2.3 mW; power consumption; power dissipation; process insensitive asynchronous logic; size 65 nm; two-step binary-search assisted time-interleaved SAR ADC architecture; Arrays; CMOS integrated circuits; Clocks; Delay; Switches; Analog-to-Digital Converter (ADC); SAR ADC; binary-search ADC; time-interleaved; two-step ADC;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4673-1555-5
Electronic_ISBN :
0886-5930
DOI :
10.1109/CICC.2012.6330695
