An uncalibrated 2MHz, 6mW, 63.5dB SNDR discrete-time input VCO-based ΔΣ ADC

Author

Hamilton, Joseph ; Yan, Shouli ; Viswanathan, T.R.

Author_Institution

Univ. of Texas, Austin, TX, USA

fYear

2012

fDate

9-12 Sept. 2012

Firstpage

1

Lastpage

4

Abstract

A 63.5dB, 2MHz bandwidth ΔΣ ADC using two ICOs pseudo-differentially as an integrator/quantizer and a combined front-end switched-capacitor V-I converter and feedback DAC in 0.18μm without performance-enhancing calibration is presented. A novel high-linearity, temperature-independent, and voltage-independent ring oscillator architecture provides a high resolution quantizer output, and a digital ΔΣ loop truncates this for a 17-level feedback DAC. The custom portion of the design consumes 6.08mW of analog power from a 1.8V supply and occupies 0.152mm².

Keywords

digital-analogue conversion; sigma-delta modulation; switched capacitor networks; voltage-controlled oscillators; ICO; bandwidth 2 MHz; feedback DAC; front-end switched-capacitor V-I converter; integrator/quantizer; performance-enhancing calibration; power 6 mW; ring oscillator architecture; uncalibrated SNDR discrete-time input VCO-based ΔΣ ADC; voltage 1.8 V; Linearity; Modulation; Radiation detectors; Ring oscillators; Switches; Tuning;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2012 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4673-1555-5

Electronic_ISBN

0886-5930

Type

conf

DOI

10.1109/CICC.2012.6330700

Filename

6330700