A partition based methodology for simulation acceleration of digital VLSI circuits using FPGAs

With rise in sophistication of digital VSLI designs, chips are being fabricated with millions of transistors involving large RTL codes. This leads to numerous problems in verification of the design because of the dramatic increase in the simulation run time. Therefore, software verification of large ASICs and system-on-chip are not preferred. Simulation assisted by special hardware and tools are gathering wide spread acceptance. The latest generation of FPGAs offers compelling platforms for hardware acceleration of computationally intensive software algorithms. The current work deals with simulation acceleration through circuit partitioning and FPGA based prototyping. The scheme has been verified on ISCAS´89 benchmark circuits.