Title :
A current reference pre-charged zero-crossing pipeline-SAR ADC in 65nm CMOS
Author :
Kuppambatti, Jayanth ; Kinget, Peter R.
Author_Institution :
Columbia Univ., New York, NY, USA
Abstract :
Using a current reference pre-charge technique, the need for power hungry low impedance voltage reference buffers is eliminated in a zero-crossing pipeline-SAR ADC. The 40MS/s ADC prototype, implemented in a 65nm CMOS process, achieves an SFDR/SDR/SNDR of 70dB/66dB/59.5dB at Nyquist, while occupying 0.95mm2 and consuming 4.5mW from a 1.35V supply, requiring no additional power for reference buffers.
Keywords :
CMOS integrated circuits; analogue-digital conversion; CMOS; SAR ADC; SDR; SFDR; SNDR; current reference precharged technique; low impedance voltage reference buffer; power 4.5 mW; size 65 nm; voltage 1.35 V; zero-crossing pipeline; CMOS integrated circuits; Calibration; Capacitors; Clocks; Jitter; Noise; Pipelines;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4673-1555-5
Electronic_ISBN :
0886-5930
DOI :
10.1109/CICC.2012.6330701
