A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling

Author

Ha, Hyunsoo ; Suh, Yunjae ; Lee, Seon-Kyoo ; Park, Hong-June ; Sim, Jae-Yoon

Author_Institution

Pohang Univ. of Sci. & Technol.(POSTECH), Pohang, South Korea

fYear

2012

fDate

9-12 Sept. 2012

Firstpage

1

Lastpage

4

Abstract

This paper presents a low-power resistive sensor interface circuit with correlated double sampling which reduces the effect of amplifier offset and enables time-interleaved single-to-differential sampling. The proposed sampling scheme, used with a 12b SAR-type analog-to-digital converter, effectively doubles the input signal and improves linearity. The fabricated chip in 0.13μm CMOS demonstrates a sampling rate of 1-kS/s and a dynamic range of 117dB with a maximum conversion error of 0.32-percent while consuming only 11.3-μW from single supply voltage of 0.5V.

Keywords

CMOS integrated circuits; analogue-digital conversion; sensors; CMOS; SAR-type analog-to-digital converter; correlated double sampling; low-power resistive sensor interface circuit; power 11.3 muW; size 0.13 mum; time-interleaved single-to-differential sampling; voltage 0.5 V; CMOS integrated circuits; Calibration; Dynamic range; Electrical resistance measurement; Resistance; Resistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2012 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4673-1555-5

Electronic_ISBN

0886-5930

Type

conf

DOI

10.1109/CICC.2012.6330702

Filename

6330702