Title :
Low frequency dithering technique for linearization of voltage mode class-D amplifiers
Author :
Malekzadeh, F.A. ; Mahmoudi, R. ; van Roermund, Arthur
Author_Institution :
Electr. Eng. Dept., Univ. of Waterloo, Waterloo, ON, Canada
Abstract :
This paper introduces a novel technique for simultaneous linearity and efficiency enhancement of class-D amplifiers by combining a low frequency sinusoid, known as dither, with a bandpass signal. The proposed technique improves the linearity due to dither averaging effect, and power efficiency, due to the reduction of reactive loss. The feasibility of the idea is verified through realization and measurement of a 65nm TSMC CMOS voltage mode class-D amplifier operating at 1 GHz. The drain efficiency is enhanced from 19.2 to 37 percent, while providing ACPR of -33dBc for the first adjacent WCDMA channel.
Keywords :
CMOS analogue integrated circuits; UHF amplifiers; UHF integrated circuits; low-power electronics; ACPR; TSMC CMOS voltage mode class-D amplifier; adjacent WCDMA channel; bandpass signal; dither averaging effect; efficiency 19.2 percent to 37 percent; frequency 1 GHz; low frequency dithering technique; low frequency sinusoid; low voltage mode class-D amplifier linearization; power efficiency; reactive loss reduction; size 65 nm; Band-pass filters; CMOS integrated circuits; Frequency measurement; Linearity; Multiaccess communication; Pulse width modulation; Voltage measurement; PAPR; Power amplifiers; class-D; dither; efficiency; linearity; load pull measurements;
Conference_Titel :
Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4673-1552-4
Electronic_ISBN :
978-1-4673-1551-7
DOI :
10.1109/SiRF.2013.6489431
