DocumentCode :
180771
Title :
IP-level implementation of a resistance-based physical unclonable function
Author :
Ismari, Dylan ; Plusquellic, Jim
Author_Institution :
Univ. of New Mexico, Albuquerque, NM, USA
fYear :
2014
fDate :
6-7 May 2014
Firstpage :
64
Lastpage :
69
Abstract :
A complete on-chip implementation of a bit generation engine using a physical unclonable function is presented in this paper. The bit generation engine, called the JellyFishPUF (JFP), provides keying material for encryption, authentication bitstrings for anti-counterfeiting and true random number generation. JFP utilizes a Physical Unclonable Function that is based on resistance variations in metals and transistors. JFP is fully implemented as a layout in an area of 0.125 mm2 using a 65 nm technology, which includes a 2KB SRAM for public data storage. The bitstrings produced from Monte Carlo SPICE-level simulations of the entropy source in combination with logic simulations of the digital engine are evaluated with respect to randomness, uniqueness and stability metrics across a wide range of temperature and voltage corners.
Keywords :
Monte Carlo methods; SRAM chips; cryptography; logic circuits; microprocessor chips; random number generation; IP-level; JFP; JellyFishPUF; Monte Carlo SPICE-level simulations; SRAM; anti-counterfeiting; authentication bit strings; bit generation engine; digital engine; encryption; entropy source; logic simulations; public data storage; resistance variations; resistance-based physical unclonable function; storage capacity 2 Kbit; transistors; true random number generation; Arrays; Authentication; Delays; Engines; Entropy; Metals; Wires; Physical Unclonable Function;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Hardware-Oriented Security and Trust (HOST), 2014 IEEE International Symposium on
Conference_Location :
Arlington, VA
Print_ISBN :
978-1-4799-4114-8
Type :
conf
DOI :
10.1109/HST.2014.6855570
Filename :
6855570
Link To Document :
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