DocumentCode
1807713
Title
A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip
Author
Ickes, Nathan ; Sinangil, Yildiz ; Pappalardo, Francesco ; Guidetti, Elio ; Chandrakasan, Anantha P.
Author_Institution
Massachusetts Inst. of Technol., Cambridge, MA, USA
fYear
2011
fDate
12-16 Sept. 2011
Firstpage
159
Lastpage
162
Abstract
We describe a voltage-scalable 32b microprocessor system-on-chip (SoC) that provides both moderate peak performance (up to 82.5 MHz at 1.2 V) and extreme energy efficiency (10.2 pJ/cycle at 0.54 V) for applications with limited energy budgets and time varying processing loads. The SoC employs low-voltage 8T SRAMs operating down to an array voltage of 0.4 V. Memory access energy is further reduced by miniature (128 B) latch-based instruction and data caches. On chip clock generation and the ability to boot from a small external serial flash ROM makes for a very small overall system.
Keywords
SRAM chips; cache storage; clocks; flip-flops; low-power electronics; microprocessor chips; system-on-chip; SoC; array voltage; chip clock generation; data cache; energy efficiency; latch-based instruction; low-voltage SRAM; memory access energy; voltage 0.4 V; voltage-scalable microprocessor system-on-chip; word length 32 bit; Clocks; Memory management; Microprocessors; Program processors; Random access memory; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
ESSCIRC (ESSCIRC), 2011 Proceedings of the
Conference_Location
Helsinki
ISSN
1930-8833
Print_ISBN
978-1-4577-0703-2
Electronic_ISBN
1930-8833
Type
conf
DOI
10.1109/ESSCIRC.2011.6044889
Filename
6044889
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