Title :
A CMOS class-E power amplifier of 40-% PAE at 5 GHz for constant envelope modulation system
Author :
Yamashita, Yukihiko ; Kanemoto, Daisuke ; Kanaya, Haruichi ; Pokharel, Ramesh K. ; Yoshida, Kenta
Author_Institution :
Grad. Sch. of Inf. Sci. & Electr. Eng., Kyushu Univ., Fukuoka, Japan
Abstract :
This paper describes the design of a high-efficient class-E power amplifier (PA) for 5-GHz wireless transmitter applications using constant envelope modulation scheme in a 0.18-μm CMOS technology. The proposed class-E PA employs injection-locking technique to reduce required input power. Furthermore, cascode topology is utilized for the proposed PA in order to reduce device stress and parasitic capacitances. The proposed PA delivers 15.4-dBm saturated output power at 5.0 GHz with 40.6-% maximum power-added efficiency (PAE) for measurement.
Keywords :
CMOS analogue integrated circuits; MMIC power amplifiers; field effect MMIC; microwave measurement; radio transmitters; CMOS class-E power amplifier; CMOS technology; constant envelope modulation system; device stress reduction; efficiency 40 percent; frequency 5 GHz; high-efficient class-E power amplifier; injection-locking technique; maximum power-added efficiency; parasitic capacitances; size 0.18 mum; wireless transmitter applications; CMOS integrated circuits; Capacitance; MOSFET; Power amplifiers; Power generation; Stress; Topology; CMOS; cascode; class-E; injection-locking (IL); power amplifier (PA); power-added efficiency (PAE);
Conference_Titel :
Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4673-1552-4
Electronic_ISBN :
978-1-4673-1551-7
DOI :
10.1109/SiRF.2013.6489434
