A 1.2–6 Gb/s, 4.2 pJ/bit Clock & Data Recovery circuit with high jitter tolerance in 0.14μm CMOS

In this paper, a highly parallelized Clock & Data Recovery (CDR) architecture with phase feedback at the bit rate is presented. This parallel CDR features demultiplexing directly at the input, which reduces circuit speed requirements and enables extensive use of standard CMOS logic which only draws dynamic power, resulting in excellent power efficiency over a wide range of speeds: power consumption is below 4.6 pJ/bit between 2.4 and 6 Gbit/s. Parallel CDRs have limited loop bandwidth and jitter tolerance due to latency in the phase-feedback loop. Our architecture solves this problem by applying feedback at the bit rate, resulting in jitter tolerance beyond 4.3 UI at 1 MHz.