Simple parallel weighted order statistic filter implementations

Author

Avedillo, María J. ; Quintana, José M. ; Rodriguez-Villegas, Esther

Author_Institution

Centro Nacional de Microelectron., Inst. de Microelectron. de Sevilla, Spain

Volume

4

fYear

2002

fDate

2002

Abstract

This paper describes a simple parallel architecture for the implementation of Weighted Order Statistic Filters (WOS), an. important class of digital nonlinear filters. The new architecture combines the design easiness of stack architectures with the area efficiency of those based in ordering matrices. It decomposes the M-valued signals into a reduced number of binary signals which are filtered by identical Boolean logic circuits. Both area-efficient and fast implementations are obtained straight-forward from filter specifications. The design of a complex WOS filter is described. Results show a sample frequency over 60 MHz in a 0.35 μm CMOS technology.

Keywords

CMOS digital integrated circuits; VLSI; digital filters; integrated circuit design; logic design; nonlinear filters; parallel architectures; 0.35 micron; 60 MHz; Boolean logic circuits; CMOS technology; M-valued signals; VLSI implementation; area-efficient implementations; binary signals; digital nonlinear filters; fast implementations; parallel architecture; weighted order statistic filter; Additive noise; Electronic mail; Frequency; Logic circuits; Matrix decomposition; Noise reduction; Nonlinear filters; Parallel architectures; Statistics; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010529

Filename

1010529