Title :
A study of robustness and coupling-noise immunity on simultaneous data transfer CDMA bus interface
Author :
Takahashi, Masaru ; Tan, Boon-Keat ; Iwamura, Hiroshi ; Matsuoka, Toshimasa ; Taniguchi, Kenji
Author_Institution :
Dept. of Electron. & Inf. Syst., Osaka Univ., Japan
Abstract :
We had proposed a novel CDMA based bus interface which features multi-bit simultaneous data transmission as a short range bus interface. This paper explores the limitation of CDMA bus interface, in terms of its coupling noise immunity based on a first order mathematical BER model. Besides coupling noise, other physical effects of circuit implementation such as process variation and clock skews have been considered. The simulation results at 50 MHz yields that using code length of 128, MB-CDMA bus interface is capable of 60 parallel transmission of 3-bits data, achieving 70 Mbps transmission which is larger than conventional TDMA based Sonic bus. The above result, obtained under random coupling noise with 2 times transmitting signal amplitude, reveals bit error rate below 10-20.
Keywords :
VLSI; code division multiple access; digital integrated circuits; error statistics; high-speed integrated circuits; integrated circuit noise; system buses; 50 MHz; 70 Mbit/s; CDMA based bus interface; VLSI implementation; bit error rate; circuit implementation; clock skews; coupling noise immunity; first order mathematical BER model; multi-bit simultaneous data transmission; process variation; short range bus interface; Bit error rate; Circuit noise; Circuit simulation; Clocks; Coupling circuits; Data communication; Mathematical model; Multiaccess communication; Noise robustness; Time division multiple access;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010530
