Title :
Optimization of a foundry compatible 0.18 μm CMOS RF and mixed single process
Author :
Keating, Richard A. ; Kordesch, Albert V. ; Huei, See Guan
Author_Institution :
Proc. Int. Group, Silterra Sdn. Bhd. Wafer Foundry, Kedah, Malaysia
Abstract :
Demand for mixed signal and RF devices on 0.18 μm CMOS silicon is driving the Foundry industry to rapidly incorporate these additional modules. This paper reports on the electrical characteristics and optimization of four mixed signal devices. Using a modular approach, Deep N-well isolated RF transistors, Native transistors, Inductors, and MIM capacitors were successfully integrated into our major Foundry Compatible 0.18 μm CMOS Logic process, without adversely affecting the digital devices. Twenty-nine different inductor structures were built and evaluated. The presence of Deep N-well implant under the inductors greatly reduced Qpeak. Self Resonance Frequency was dominated by factors controlling capacitive coupling to the substrate (line width, number of coil turns).
Keywords :
CMOS logic circuits; elemental semiconductors; silicon; 0.18 micron; CMOS logic process; CMOS silicon; MIM capacitors; RF devices; RF transistors; complementary metal-oxide-semiconductor; digital devices; electrical characteristics; inductors; metal-insulator-metal capacitors; mixed signal devices; self resonance frequency; CMOS logic circuits; CMOS process; Electric variables; Foundries; Inductors; Logic devices; MIM capacitors; RF signals; Radio frequency; Silicon;
Conference_Titel :
Semiconductor Electronics, 2002. Proceedings. ICSE 2002. IEEE International Conference on
Print_ISBN :
0-7803-7578-5
DOI :
10.1109/SMELEC.2002.1217856