A 4GHz-bandwidth op-amp-free track-and-hold and 6-bit flash ADC in 45nm SOI CMOS

Author

Chen, M.W. ; Tian, D. ; Phatak, Sai ; Carley, L.R. ; Ricketts, David S.

Author_Institution

Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

2013

fDate

21-23 Jan. 2013

Firstpage

126

Lastpage

128

Abstract

A 2GS/s 6-bit flash sub-ADC with an op-amp free track-and-hold (T&H) for use in an 8GS/s 4-way time-interleaved ADC was implemented in 45nm SOI CMOS. The T&H utilizes a passive charge sharing technique and achieves a 4GHz input bandwidth at 2GS/s clock rate without an op-amp. The flash sub-ADC consumes 74mW at 2GS/s and occupies an area of 0.2mm². The measured INL and DNL are -0.9/1.0LSB and -1.35/0.9LSB, respectively. The sub-ADC SNDR is 33.9dB at 2GS/s with a 125MHz input and 30.6dB with a 4GHz input.

Keywords

CMOS integrated circuits; analogue-digital conversion; sample and hold circuits; silicon-on-insulator; SOI CMOS; analog-to-digital convertors; bandwidth 125 MHz; bandwidth 4 GHz; operational amplifiers; passive charge sharing technique; power 74 mW; silicon-on-insulator; size 45 nm; time-interleaved ADC; track-and-hold; word length 6 bit; Bandwidth; CMOS integrated circuits; Calibration; Capacitance; Clocks; Latches; Preamplifiers; Analog-to-digital converter (ADC); SOI CMOS; calibration; flash ADC; track-and-hold;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on

Conference_Location

Austin, TX

Print_ISBN

978-1-4673-1552-4

Electronic_ISBN

978-1-4673-1551-7

Type

conf

DOI

10.1109/SiRF.2013.6489454

Filename

6489454