Area- and energy-efficient high-throughput LDPC decoders with low block latency

The challenge in designing LDPC decoders is the efficient realization of the global communication between the two basic component types of such a decoder. Tight timing constraints in high-performance applications demand for a dedicated interconnect, which in general negatively affects the decoder features, especially the silicon area. Various approaches to reduce this impact have been discussed in literature which typically consider only a few if not just one level of the CMOS design process. However, for hardware efficient implementations a joint optimization on all design levels is mandatory. In this work we exemplarily present such an optimization for a (6, 32)-regular (2048, 1723) LDPC code ranging from an analysis of fix-point realizations of the decoding algorithm to an optimization on physical implementation level which can be applied to other codes, as well. The resulting decoder was implemented in a 40-nm CMOS technology. Circuit simulations of extracted netlists reveal an ATE-complexity reduction of more than one order of magnitude compared to known decoder implementations.