A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS

Author

Agarwal, Amit ; Hsu, Steven ; Mathew, Sanu ; Anders, Mark ; Kaul, Himanshu ; Sheikh, Farhana ; Krishnamurthy, Ram

Author_Institution

Circuits Res. Lab., Intel Corp., Hillsboro, OR, USA

fYear

2011

fDate

12-16 Sept. 2011

Firstpage

83

Lastpage

86

Abstract

A 128-entry × 128b content addressable memory (CAM) design enables 145ps search operation in 1.0V, 32nm high-k metal-gate CMOS technology. A high-speed 16b wide dynamic AND match-line, combined with a fully static search-line and swapped XOR CAM cell simulations show a 49% reduction of search energy at iso-search delay of 145ps over an optimized high-performance conventional NOR-type CAM design, enabling 1.07fJ/bit/search operation. Scaling the supply voltage of the proposed CAM enables 0.3fJ/bit/search with 1.07ns search delay at 0.5V.

Keywords

CMOS memory circuits; NOR circuits; content-addressable storage; NOR-type CAM design; XOR CAM cell simulation; high-k metal-gate CMOS technology; high-speed wide-AND match-line content addressable memory; isosearch delay; size 32 nm; time 1.07 ns; time 145 ps; voltage 0.5 V; voltage 1.0 V; Associative memory; CMOS integrated circuits; Clocks; Computer aided manufacturing; Delay; Logic gates; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC (ESSCIRC), 2011 Proceedings of the

Conference_Location

Helsinki

ISSN

1930-8833

Print_ISBN

978-1-4577-0703-2

Electronic_ISBN

1930-8833

Type

conf

DOI

10.1109/ESSCIRC.2011.6044920

Filename

6044920