An integrated characterization and modeling methodology for CMP dielectric planarization

Efficient chip-level CMP models are required to predict dielectric planarization performance for arbitrary layouts prior to CMP. We present an integrated calibration and modeling methodology for oxide planarization which extends previous work in several important ways. First, we describe improved characterization methods for model calibration, including new short flow test masks and simplified planarization model parameter extraction. Secondly, we present efficient physically motivated density calculation and integration with a planarization model for prediction of oxide thickness above and between metal structures across the entire die. Predictions based on the model show excellent agreement when applied to layouts not used in model calibration