Title :
High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs
Author :
Trawka, Maciej ; Mrugalski, Grzegorz ; Mukherjee, Nandini ; Pogiel, Artur ; Rajski, J. ; Janicki, Jakub ; Tyszer, J.
Author_Institution :
Gdarisk Univ. of Technol., Gdarisk, Poland
Abstract :
The paper presents a high-speed serial interface between external tester and Embedded Deterministic Test (EDT) compression logic hosted by SoC designs. With only a single bidirectional link, the system is capable of feeding distributed heterogeneous cores with hundreds of test channels. Moreover, it synergistically supports EDT bandwidth management to improve the overall test performance. A detailed study indicates a high potential of the serial EDT approach to handle large multicore SoC designs by deploying only a single serial interface and completing the entire test for stuck-at faults in less than one second. Experiments conducted with the help of FPGA -- based evaluation platform confirm feasibility and a high effectiveness of the proposed solution.
Keywords :
fault diagnosis; field programmable gate arrays; high-speed integrated circuits; integrated circuit design; integrated circuit testing; logic testing; system-on-chip; EDT bandwidth management; EDT compression logic; FPGA-based evaluation platform; external tester; feeding distributed heterogeneous cores; high-speed serial embedded deterministic test; high-speed single serial interface; large multicore SoC designs; overall test performance improvement; single bidirectional link; stuck-at faults; system-on-chip designs; test channels; Bandwidth; Clocks; Phase locked loops; Pins; Synchronization; System-on-chip; Universal Serial Bus;
Conference_Titel :
Test Symposium (ATS), 2014 IEEE 23rd Asian
Conference_Location :
Hangzhou
DOI :
10.1109/ATS.2014.25
