An FPGA implementation of an on-line radix-4 CORDIC 2-D IDCT core

Author

Yang, Yi ; Wang, Chunyan ; Ahmad, M. Omair ; Swamy, M.N.S.

Author_Institution

Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada

Volume

4

fYear

2002

fDate

2002

Abstract

In this paper, we present a new architecture for a two-dimensional (2D) inverse discrete cosine transform (IDCT) core based on a modified radix-4 on-line CORDIC algorithm and distributed arithmetic (DA). The architecture is designed to take advantage of the "carry-free" addition property of redundant number representation and the "multiplierless" property of DA. The core operates on blocks of 8×8 pixels, with 12-bit and 9-bit precision for inputs and outputs, respectively. The proposed design is implemented on Xilinx Virtex XC2V 1000 FPGA. The test results show that the core for IDCT can operate at 100 MHz, while meeting the accuracy requirements of the CCITT H.26x standard.

Keywords

digital signal processing chips; discrete cosine transforms; distributed arithmetic; field programmable gate arrays; integrated circuit design; integrated circuit testing; logic design; logic testing; redundant number systems; signal processing; 100 MHz; CCITT H.26x standard accuracy requirements; DA multiplierless property; FPGA implementation; Xilinx Virtex XC2V 1000 FPGA; carry-free addition; core blocks; distributed arithmetic; inverse discrete cosine transform core; modified radix-4 on-line CORDIC algorithm; on-line radix-4 CORDIC 2D IDCT core; redundant number representation; Arithmetic; Computer architecture; Decoding; Discrete cosine transforms; Field programmable gate arrays; Read only memory; Transform coding; Very large scale integration; Video codecs; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010569

Filename

1010569