DocumentCode
180899
Title
Silicon Evaluation of Cell-Aware ATPG Tests and Small Delay Tests
Author
Fan Yang ; Chakravarty, Sumit ; Gunda, Arun ; Wu, NaiQi ; Jianyu Ning
Author_Institution
Avago Technol., San Jose, CA, USA
fYear
2014
fDate
16-19 Nov. 2014
Firstpage
101
Lastpage
106
Abstract
This paper presents silicon results for two such proposed fault models: the cell aware fault model and the small delay defect fault model. The corresponding tests including cell-aware ATPG tests and Fast-than at-speed TDF tests are evaluated on an industrial design. Results from a high volume manufacturing experiment on a 65nm Serial Attached SCSI (SAS) RAID-On-a-Chip (ROC) device are presented. The incremental value of these fault models and tests beyond our current test flow is discussed.
Keywords
RAID; automatic test pattern generation; fault diagnosis; integrated circuit testing; peripheral interfaces; SAS ROC device; cell aware fault model; cell-aware ATPG tests; fast-than at-speed TDF tests; industrial design; serial attached SCSI RAID-on-a-chip device; silicon evaluation; silicon results; size 65 nm; small delay defect fault model; Automatic test pattern generation; Circuit faults; Clocks; Delays; Logic gates; Silicon; Transistors; Cell-aware; faster than at-speed TDF test; silicon evaluation; small delay;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium (ATS), 2014 IEEE 23rd Asian
Conference_Location
Hangzhou
ISSN
1081-7735
Type
conf
DOI
10.1109/ATS.2014.29
Filename
6979084
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