Programmable video clock synthesizer with sub 0.5 ns drift

This paper presents a video clock synthesizer. The block is programmable; it accepts input frequencies from 20 kHz to 5 MHz and produces output frequencies up to 200 MHz. The synthesizer is designed to reduce phase drift in the output clock. This parameter is critical in video applications because large phase drift can result in the loss of pixel data. The phase drift was measured at less than 0.5 ns for all input clocks greater than 30 kHz. This represents an improvement of a factor of 6 on measurements reported on a related synthesizer in a recent publication. Another key parameter of the synthesizer is VDD sensitivity of the open loop VCO. This is particularly important in noisy VLSI applications. This sensitivity was measured at 0.18%/volt, which makes the device suitable for integration. The synthesizer area is 1.2 mm² (0.25 μm CMOS) and it consumes 17 mW at 110 MHz.