Exploit Dynamic Voltage and Frequency Scaling for SoC Test Scheduling under Thermal Constraints

Increasing power density and thermal hotspots has become a major problem for integrated circuits. The problem is exacerbated when applying tests to a System-on-Chip (SoC). Running a test individually may exceed the given temperature threshold. So scheduling tests to reduce the test application time (TAT) while keep the cores thermally safe has become a key issue. Dynamic Voltage and Frequency Scaling (DVFS) has been widely used in modern IC devices to control power and temperature. We exploit such features for thermal-aware test scheduling and propose a method to efficiently determine the scaling factor which leads to optimized TAT without violating the thermal constraints. The proposed method can also be used to efficiently calculate the maximum temperature certain tests can achieve when DVFS is applied. After formulating the problem into an MILP model, experimental results on ITC´02 benchmarks showed that DVFS can be used to deal with power intensive tests efficiently and exploiting such features can achieve up to 16.37% reduction of TAT.