Title :
Timing Evaluation Tests for Scan Enable Signals with Application to TDF Testing
Author :
Jie Zou ; Chao Han ; Singh, Adit D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA
Abstract :
Scan based transition delay fault (TDF) tests are generally applied in the launch-on-capture (LOC) mode because the scan enable control signal broadcast to all flip-flops on the die is expensive to implement as a fast switching signal needed to support at-speed launch-on-shift (LOS) tests. However, there is mounting evidence that even when applied at much slower speeds, LOS tests often detect a significant fraction of the timing defects, including many unique failures that are missed by LOC test. This suggests the use of combined LOC and LOS test to increase the TDF coverage beyond that attainable by LOC tests alone. However, to maximize the detection of real delay defects, the LOS tests must be applied at the fastest possible speed (up to the functional clock rate) within the timing limitations of the scan enable. To support such testing, in this paper we present the first test technique to reliably evaluate the switching speed of the scan enable signal. This can vary significantly for individually manufactured instances of the same design due to normal process variations at advanced technology nodes, amplified by near quadratic delays in the long interconnect lengths of this broadcast signal. Once the scan enable speed is determined, LOS tests can be applied at the fastest, most effective speed. Furthermore, the availability of this effective low cost LOS test capability also facilitates the partitioning of the scan flip flops through the use of multiple scan enable signals that apply the delay test in mixed LOS and LOC modes in the different partitions. We show that the use of only two scan enable signals in such an approach can significantly increase TDF test coverage, and raise it very close to the highest possible that is achievable only by enhanced scan.
Keywords :
flip-flops; integrated circuit testing; timing; LOC mode; TDF test coverage; at-speed LOS tests; at-speed launch-on-shift tests; broadcast signal; control signal broadcast; fast switching signal; flip-flops; interconnect lengths; launch-on-capture mode; near quadratic delays; process variations; real delay defects detection; scan based TDF tests; scan based transition delay fault tests; scan enable signal; scan enable speed; scan flip flops; switching speed; timing defects; timing limitations; Circuit faults; Clocks; Delays; Flip-flops; Switches; Testing; LOC; LOS; Scan enable signal; TDF;
Conference_Titel :
Test Symposium (ATS), 2014 IEEE 23rd Asian
Conference_Location :
Hangzhou
DOI :
10.1109/ATS.2014.59