DocumentCode
1809385
Title
Incorporation of input glitches into power macromodeling
Author
Liu, Xun ; Papaefthymiou, Marios C.
Author_Institution
Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
Volume
4
fYear
2002
fDate
2002
Abstract
Previous research on power macromodeling has always assumed glitch-free input signals. However, in an actual operating environment, the input signals of a circuit can contain glitches, which are generated by the previous stage of circuitry. In this paper, we investigate the impact of input glitches on the power dissipation of a circuit. Specifically, we show that the frequency and average duration of input glitches are two important factors affecting the overall power consumption. Input glitches can also increase output glitching by a surprisingly large amount. We present a simple yet effective analytical power macromodeling approach incorporating the effects of input glitching. In experiments with ISCAS-85 benchmark circuits, the average error of the proposed technique is 4.44%.
Keywords
CMOS logic circuits; circuit simulation; combinational circuits; integrated circuit modelling; logic simulation; ISCAS-85 benchmark circuits; analytical power macromodeling approach; average error; average glitch duration; combinational static CMOS circuits; input glitch frequency; input glitch incorporation; output glitching; overall power consumption; power dissipation; power macromodeling; simulation setup; Circuit simulation; Computer architecture; Energy consumption; Frequency; Power dissipation; Power generation; Signal generators; Signal mapping; Statistics; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN
0-7803-7448-7
Type
conf
DOI
10.1109/ISCAS.2002.1010590
Filename
1010590
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