Power hardware-in-the-loop (PHIL) based on FPGA

Nowadays, to improve power quality and power demand, several studies point to the use of Active Power Line Conditioners (APLCs) and Distributed Generation (DG), both based on power electronic devices. Considering various distributed power devices with cooperative operation, the strategies evaluation to compensate harmonics and correct power factor (PF) in Electric Power System (EPS) is only possible to be investigated by simulation. In this work, it is proposed a Power Hardware-in-the-loop (PHIL) system for testing the APLCs operation. The proposed PHIL system can evaluate the performance of the APLC control strategies and EPS dynamic response under APLC operation. Furthermore, the same platform can be used to integrating DGs with the EPS as it also uses power electronic devices.