Title :
A 4mW 1 GS/s continuous-time ΔΣ modulator with 15.6MHz bandwidth and 67 dB dynamic range
Author :
Jain, Ankesh ; Venkateswaran, Muthusubramanian ; Pavan, Shanthi
Author_Institution :
Indian Inst. of Technol. Madras, Chennai, India
Abstract :
We present architectural and circuit design details of a single-bit continuous-time ΔΣ modulator in 0.13 μm CMOS sampling at 1 GS/s. The “assisted opamp technique” is used to obtain high linearity with low power consumption. Analysis of the effects of timing-skew between the feedback and assistant DACs is given. The converter achieves a dynamic range of 67 dB in 15.6 MHz bandwidth and consumes 4 mW. The figure of merit (FOM) of the modulator is 93 fJ/level.
Keywords :
CMOS analogue integrated circuits; delta-sigma modulation; operational amplifiers; CMOS sampling; DAC; FOM; architectural circuit design; assisted opamp technique; bandwidth 15.6 MHz; figure of merit; gain 67 dB; power 4 mW; power consumption; single-bit continuous-time ΔΣ modulator; size 0.13 mum; timing-skew effect; Bandwidth; Dynamic range; Linearity; Modulation; Signal to noise ratio; Timing;
Conference_Titel :
ESSCIRC (ESSCIRC), 2011 Proceedings of the
Conference_Location :
Helsinki
Print_ISBN :
978-1-4577-0703-2
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2011.6044956
