VLSI architectures for the implementation of the Wigner distribution

The Wigner distribution is a valuable tool for time-frequency signal analysis. Two different VLSI architectures for the real-time implementation of the Wigner distribution algorithm are proposed in this paper, with the objective of pointing out various computational issues that are involved. Reduction of the computational load of the algorithm, as well as reduction of the memory requirements has been achieved mostly by applying simple trigonometric properties to the original expression of the algorithm. The addressing schemes to access the memory blocks are also proposed.