DocumentCode
1809594
Title
A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration
Author
Vengattaramane, Kameswaran ; Borremans, Jonathan ; Steyaert, Michiel ; Craninckx, Jan
Author_Institution
SSET-Wireless, IMEC, Leuven, Belgium
fYear
2011
fDate
12-16 Sept. 2011
Firstpage
275
Lastpage
278
Abstract
This paper presents a standard-cell based All-Digital Time-to-Digital Converter with reconfigurable resolution reaching sub-gate delay. The architecture based on spatial oversampling is implemented with an automated digital design flow. It features a robust online background calibration scheme for gain tracking. A 90 nm prototype chip achieves [39-14] ps effective resolution consuming [1-8] mA, in an area of only 0.26 mm2.
Keywords
calibration; convertors; phase detectors; all-digital time-to-digital converter; gain tracking; on-line background calibration; reconfigurable resolution; spatial oversampling; standard cell; sub-gate delay; Calibration; Computer architecture; Delay; Phase locked loops; Quantization; Radiation detectors; Spatial resolution;
fLanguage
English
Publisher
ieee
Conference_Titel
ESSCIRC (ESSCIRC), 2011 Proceedings of the
Conference_Location
Helsinki
ISSN
1930-8833
Print_ISBN
978-1-4577-0703-2
Electronic_ISBN
1930-8833
Type
conf
DOI
10.1109/ESSCIRC.2011.6044960
Filename
6044960
Link To Document