A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration

This paper presents a standard-cell based All-Digital Time-to-Digital Converter with reconfigurable resolution reaching sub-gate delay. The architecture based on spatial oversampling is implemented with an automated digital design flow. It features a robust online background calibration scheme for gain tracking. A 90 nm prototype chip achieves [39-14] ps effective resolution consuming [1-8] mA, in an area of only 0.26 mm².