• DocumentCode
    1809643
  • Title

    RISC3202: A Software Configuration Dual-Issue/Dual-Core Microprocessor

  • Author

    Yao, Yingbiao ; Wang, Bin ; Zhang, Jianwu ; Yao, Qingdong

  • Author_Institution
    Hangzhou Dianzi Univ., Hangzhou
  • fYear
    2007
  • fDate
    18-21 Sept. 2007
  • Firstpage
    963
  • Lastpage
    968
  • Abstract
    RISC-based processors have been extended into almost all kinds of embedded applications. These applications have different features thus require different processor architectures. Thus, we have developed a dual-core/dual-issue mixed micro-architecture processor named as RISC3202 which is based on two simple RISC cores. On the one hand, RISC3202 is an in-order dual-issue superscalar processor for single-thread applications. On the other hand, RISC3202 is a shared-memory dual-core processor for multiple-thread applications. The work mode of RISC3202 is configurable during running programs. Therefore, RISC3202 fits well for different features of target applications and its hardware usage rate is always high.
  • Keywords
    microprocessor chips; shared memory systems; RISC-based processors; RISC3202; dual-core microprocessor; dual-core-dual-issue mixed micro-architecture processor; dual-issue microprocessor; in-order dual-issue superscalar processor; multiple-thread applications; processor architectures; shared-memory dual-core processor; software configuration; Application software; Costs; Frequency; Hardware; Microarchitecture; Microprocessors; Parallel processing; Pipelines; Process design; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Network and Parallel Computing Workshops, 2007. NPC Workshops. IFIP International Conference on
  • Conference_Location
    Liaoning
  • Print_ISBN
    978-0-7695-2943-1
  • Type

    conf

  • DOI
    10.1109/NPC.2007.49
  • Filename
    4351611