Automatic generated built-in-self-test for embedded memory

Author

Banerjee, Shibaji ; Mukhopadhyay, Debdeep ; Chowdhury, Dipanwita Roy

Author_Institution

Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India

fYear

2004

fDate

20-22 Dec. 2004

Firstpage

377

Lastpage

380

Abstract

Embedded memory test is becoming an important issue in system-on-chip (SOC) development. Direct access of memory cores from the limited number of I/O pins is usually not feasible. Built-in-self-test (BIST) is rapidly becoming the most acceptable solution. A BIST design for embedded DRAMs is proposed. The BIST circuit is on-line programmable for its NPSF test algorithms. Experimental results show that the present BIST design is cost effective.

Keywords

DRAM chips; built-in self test; integrated circuit testing; interactive programming; system-on-chip; I-O pin; NPSF test algorithm; SOC; automatic generated BIST; built-in-self-test; dynamic random access memory; embedded DRAM; neighborhood pattern sensitive fault; on-line programming; system-on-chip; Bandwidth; Built-in self-test; Circuit faults; Circuit testing; Computer architecture; Costs; Pins; Random access memory; System testing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

India Annual Conference, 2004. Proceedings of the IEEE INDICON 2004. First

Print_ISBN

0-7803-8909-3

Type

conf

DOI

10.1109/INDICO.2004.1497776

Filename

1497776

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1809737