DocumentCode
1810083
Title
A 6Gbps 3mW optical receiver with DCOC-combined ATC in 65nm CMOS
Author
Akita, Ippei ; Tsubouchi, Yuta ; Itakura, Tetsuro ; Nishigaki, Michihiko ; Uemura, Hiroshi ; Furuyama, Hideto ; Shibata, Hideki
Author_Institution
Corp. R&D Center, Toshiba Corp., Kawasaki, Japan
fYear
2011
fDate
12-16 Sept. 2011
Firstpage
343
Lastpage
346
Abstract
This paper presents a 0.48-mW/Gbps optical receiver in a 65-nm CMOS process. The receiver includes a tran-simpedance amplifier (TIA) with a DC offset canceler (DCOC) combined with an autothreshold controller (ATC) function for providing low-power, area-efficient single-ended-to-differential conversion. The fabricated 6-Gbps optical receiver consumes 2.86-mW power and achieves less than -3.8-dBm sensitivity at a BER of 10-11.
Keywords
CMOS integrated circuits; operational amplifiers; optical receivers; CMOS; DC offset canceler; DCOC-combined ATC; autothreshold controller function; bit rate 6 Gbit/s; optical receiver; power 3 mW; size 65 nm; transimpedance amplifier; Bit error rate; CMOS integrated circuits; Optical buffering; Optical receivers; Optical sensors; Optical variables measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
ESSCIRC (ESSCIRC), 2011 Proceedings of the
Conference_Location
Helsinki
ISSN
1930-8833
Print_ISBN
978-1-4577-0703-2
Electronic_ISBN
1930-8833
Type
conf
DOI
10.1109/ESSCIRC.2011.6044977
Filename
6044977
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