Title :
Simulation and performance evaluation of a modularly configurable attached processor
Author :
Yi-Chieh Chang ; Gibson, Glenn ; Ayala, Claudia
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., El Paso, TX, USA
Abstract :
A new architecture for high-performance parallel attached processors is studied in this paper. The unique features are that the attached processor can be configured to match a set of algorithms and its memory controllers can be programmed to fit the access patterns required by the algorithms. As a result, high utilization of the processing logic for given sets of algorithms can be obtained. A simulator with interactive graphic interface is designed to study the performance of the proposed architecture. An example based on matrix multiplication is used for illustration. The simulation results show that a sustained execution rate as high as 95% of the peak speed for matrices with a size of 128×128 can be achieved in the proposed attached processor architecture. If CMOS technology is chosen to implement the MCAP architecture, a sustained speed of 190 MFLOPS can be obtained for matrix multiplication with four multipliers and four adders
Keywords :
digital simulation; parallel architectures; performance evaluation; CMOS technology; access patterns; interactive graphic interface; memory controllers; modularly configurable attached processor; parallel attached processors architecture; performance evaluation; processing logic; simulation; Algorithm design and analysis; Arithmetic; CMOS process; CMOS technology; Computational modeling; Computer architecture; Graphics; Logic; Operating systems; Pattern matching;
Conference_Titel :
Parallel and Distributed Systems, 1994. International Conference on
Conference_Location :
Hsinchu
Print_ISBN :
0-8186-6555-6
DOI :
10.1109/ICPADS.1994.590056
