Title :
A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications
Author :
Pontikakis, Bill ; Nekili, Mohamed
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
Abstract :
In this paper, a pulse-clocked double edge-triggered D-flip-flop (PDET) is proposed. The PDET uses a split-output TSPC latch and when clocked by a short pulse train acts like a double edge-triggered flip-flop. The new double edge-triggered flip-flop uses only eight transistors with only one N-type transistor being clocked. Compared to other double edge-triggered flip-flops, PDET offers advantages in terms of speed, power, and area. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge-triggered flip-flops. Simulations are performed using HSPICE in CMOS 0.5 μm technology. This design is suitable for high-speed, low-power CMOS VLSI design applications.
Keywords :
CMOS logic circuits; SPICE; circuit simulation; flip-flops; high-speed integrated circuits; integrated circuit design; logic design; low-power electronics; 0.5 micron; HSPICE simulations; area-speed-power product; clocked transistor number; double edge-triggered pulse-clocked TSPC D flip-flop; flip-flop speed; high-speed low-power CMOS VLSI design; low-power VLSI design; power consumption; short pulse train clocking; split-output TSPC latch; total transistor count; CMOS technology; Circuit simulation; Clocks; Energy consumption; Flip-flops; Inverters; Latches; Pulse circuits; Pulse generation; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010650
