• DocumentCode
    1810417
  • Title

    Pipelined architecture of reconfigurable specialised processors for a real-time image data pre-processing

  • Author

    Wiatr, Kazimierz

  • Author_Institution
    Inst. of Electron., AGH Tech Univ., Warsaw, Poland
  • Volume
    1
  • fYear
    1996
  • fDate
    14-18 Oct 1996
  • Firstpage
    649
  • Abstract
    This paper presents a multiprocessor unit for fast video image data pre-processing in real time application. The author made a pipelined multiprocessor architecture from specialised hardware processors. This paper presents a reconfigurable specialised hardware processor for this pipelined architecture. The universal reconfigurable processor is implementated in Xilinx FPGA
  • Keywords
    application specific integrated circuits; digital signal processing chips; multiprocessing systems; pipeline processing; real-time systems; reconfigurable architectures; video signal processing; Xilinx FPGA; fast video image data pre-processing; pipelined multiprocessor architecture; real-time image data pre-processing; reconfigurable specialised hardware processor; universal reconfigurable processor; Clocks; Field programmable gate arrays; Filtering algorithms; Hardware; Image processing; Pipelines; Pixel; Signal analysis; Signal processing; TV;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing, 1996., 3rd International Conference on
  • Conference_Location
    Beijing
  • Print_ISBN
    0-7803-2912-0
  • Type

    conf

  • DOI
    10.1109/ICSIGP.1996.567347
  • Filename
    567347
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1810417