Current-sensing completion detection method for standard cell based digital system design

Author

Lampinen, Harri ; Vainio, Olli

Author_Institution

Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland

Volume

5

fYear

2002

fDate

2002

Abstract

This paper shows how the current-sensing completion detection (CSCD) method can be applied for standard cell based digital system design. With the proposed method, conventional synchronous CMOS logic circuit blocks can easily be modified for self-timed asynchronous operation. To illustrate the usage of the method a self-timed CSCD multiplier-accumulator (MAC) was constructed. Simulation results and VHDL synthesized layouts of the CSCD MAC show that the CSCD method and the various proposed design practices can be used for the construction of self-timed asynchronous logic systems.

Keywords

CMOS logic circuits; asynchronous circuits; circuit layout CAD; hardware description languages; integrated circuit layout; logic CAD; logic partitioning; logic simulation; 16-bit system; VHDL synthesized layouts; current-sensing completion detection method; self-timed CSCD multiplier-accumulator; self-timed asynchronous operation; simulation results; standard cell based digital system design; synchronous CMOS logic circuit blocks; CMOS logic circuits; CMOS technology; Clocks; Delay; Digital systems; Logic design; Logic testing; Pipelines; Registers; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010654

Filename

1010654