Title :
A fully digital delay-line based GHz-range multimode transmitter front-end in 65-nm CMOS
Author :
Nuyts, Pieter A J ; Singerl, Peter ; Dielacher, Franz ; Reynaert, Patrick ; Dehaene, Wim
Author_Institution :
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium
Abstract :
A fully digital up-converter for wireless transmission in the GHz range is presented. The system consists of a polar modulator which uses PWM for the amplitude modulator (AM). Phase modulation (PM) is implemented by shifting the carrier in time. Both the PWM and the PM are implemented using asynchronous delay lines which allow time resolutions down to 10 ps without the need for high-frequent clock signals. The system is designed to drive two class-E power amplifiers with a power combiner. It supports a continuous range of carrier frequencies starting at 946 MHz and limited upwards only by the desired resolution. The modulator has been implemented in 65-nm CMOS. Results show error vector magnitude (EVM) values between 1.24% (-38.1 dB) at 946 MHz and 3.98% (-28.0 dB) at 2.4 GHz for 64-QAM OFDM signals.
Keywords :
CMOS digital integrated circuits; OFDM modulation; power amplifiers; power combiners; quadrature amplitude modulation; radio transmitters; 64-QAM OFDM signals; CMOS; GHz-range multimode transmitter front-end; PWM; amplitude modulator; asynchronous delay lines; class-E power amplifiers; digital delay-line; digital up-converter; error vector magnitude; frequency 2.4 GHz; frequency 946 MHz; phase modulation; polar modulator; power combiner; size 65 nm; wireless transmission; Bandwidth; Delay; Delay lines; OFDM; Pulse width modulation; Radio frequency; Signal resolution;
Conference_Titel :
ESSCIRC (ESSCIRC), 2011 Proceedings of the
Conference_Location :
Helsinki
Print_ISBN :
978-1-4577-0703-2
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2011.6044990
