SRAM oriented memory sense amplifier design in 0.18 μm CMOS technology

Author

Chrisanthopoulos, A. ; Tsiatouhas, Y. ; Arapoyanni, A. ; Haniotakis, Th

Author_Institution

Adv. Silicon Solutions Div., ISD S.A, Athens, Greece

Volume

5

fYear

2002

fDate

2002

Abstract

In this paper a new two-stage sensing scheme suitable for current sensing in SRAM read operation is presented. The proposed scheme provides fast response with low silicon area requirements, since it incorporates only three transistors in the pitch of the bit lines for the sensing of the stored data in the selected memory cell. Process and temperature variation related simulations are provided in order to explore the operating range of the sensors in various conditions. In addition, comparison results are given with respect to a conventional sensing scheme. Finally, a compact layout design is presented to illustrate the area efficiency of the proposed sensing architecture.

Keywords

CMOS memory circuits; SRAM chips; integrated circuit layout; memory architecture; 0.18 micron; CMOS technology; SRAM; area efficiency; current sensing; layout design; memory sense amplifier; silicon area requirements; stored data; temperature variation related simulations; two-stage sensing scheme; CMOS technology; Capacitance; Circuit topology; Delay; Informatics; Random access memory; Silicon; Telecommunication computing; Temperature sensors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010661

Filename

1010661