A dual salicide process scalable to sub-0.25-μm CMOS technologies

Author

Lin, X.W. ; Weling, M. ; Pramanik, D.

Author_Institution

VLSI Technol. Inc., San Jose, CA, USA

fYear

1998

fDate

1-3 Jun 1998

Firstpage

93

Lastpage

95

Abstract

A novel salicide process is presented which allows for independent silicidation of source/drain areas and polysilicon gates, thus making it possible to achieve ultra-shallow junction formation with very low gate sheet resistance (R_s) for sub-0.25 μm CMOS device fabrication. Titanium was used to demonstrate this process in a 0.25 μm technology, yielding fully functional transistors with gate R_s<2 Ω/sq

Keywords

CMOS integrated circuits; electric resistance; integrated circuit interconnections; integrated circuit metallisation; integrated circuit yield; titanium compounds; 0.25 micron; CMOS device fabrication; CMOS technology; TiSi₂; dual salicide process; functional transistors; gate sheet resistance; independent silicidation; polysilicon gate silicidation; salicide process; scalable dual salicide process; source/drain area silicidation; titanium salicide; ultra-shallow junction formation; CMOS process; CMOS technology; Dielectric devices; Doping; Electrodes; Electrons; Implants; Silicidation; Strips; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 1998. Proceedings of the IEEE 1998 International

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-4285-2

Type

conf

DOI

10.1109/IITC.1998.704760

Filename

704760