DocumentCode :
1810770
Title :
Process technique for improving the tuning range in MOS varactors
Author :
Kulkarni, Jaydeep P. ; Bhat, Navakanta
Author_Institution :
Cypress Semicond. Technol. Ltd., Bangalore, India
fYear :
2004
fDate :
20-22 Dec. 2004
Firstpage :
534
Lastpage :
537
Abstract :
This paper presents a new technique to improve the tuning range of MOS varactors in conventional CMOS technology. Poly-silicon depletion effect is intentionally incorporated in the gate electrode of varactor. It is demonstrated that the tuning range increases by 60% without degradation in Q factor. The process for the proposed poly-silicon depletion effect does not require any extra process steps, except the redefinition of the appropriate masks, making this technique compatible with current CMOS technology. An analytical model for this improvement is also discussed.
Keywords :
CMOS integrated circuits; Q-factor; circuit tuning; electrodes; radiofrequency integrated circuits; silicon; varactors; MOS varactor; Q factor; RF CMOS; Si; gate electrode; poly-silicon depletion effect; tuning range; CMOS technology; Capacitance; Channel bank filters; Doping; Electrodes; MOS capacitors; Q factor; Semiconductor diodes; Silicon; Varactors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
India Annual Conference, 2004. Proceedings of the IEEE INDICON 2004. First
Print_ISBN :
0-7803-8909-3
Type :
conf
DOI :
10.1109/INDICO.2004.1497813
Filename :
1497813
Link To Document :
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