DocumentCode :
1811017
Title :
Low-power circuit advantages of the scaled accumulation FET
Author :
Murali, Raghunath ; Wang, Lihui ; Austin, Blanca L. ; Meindl, James D.
Author_Institution :
Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
Volume :
5
fYear :
2002
fDate :
2002
Abstract :
The trend toward higher clock frequencies has resulted in FETs being compared for their performance at the highest frequencies. Traditionally, the buried channel(BC) FET is considered to have more short channel effects than the normal surface channel inversion(SCI) FET and thus the BC FET is used only when absolutely needed. The same, more severe short channel effects behavior has been assumed for moderate to high-VT FETs, which find use in ultra low-power applications. However, a careful investigation both at the transistor and circuit level, reveals that the BC FET is better than the SCI FET for moderate speed, ultra low-power applications.
Keywords :
MOSFET; accumulation layers; low-power electronics; semiconductor device models; BC FET; buried channel; clock frequencies; low-power circuit; scaled accumulation FET; ultra low-power applications; Analytical models; Circuits; Clocks; Doping; FETs; Frequency; Inverters; Medical simulation; Numerical simulation; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
Type :
conf
DOI :
10.1109/ISCAS.2002.1010675
Filename :
1010675
Link To Document :
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